Increased requirements in power density and technology scaling for electronic package components have encountered considerably increased existing reliability problems in recent years, as a result of which lifetime reliability and process variation has already been elevated to the “critical challenges” category according to ITRS 2005 in the technology.
Chip lifetime reliability has traditionally been ensured through process qualification and sorting out of defective chips through accelerated degradation techniques like process burn-in. The utilization of structural duplication is considered as another standard technique for dealing with lifetime reliability issues; however, the corresponding required overhead in terms of increased cost, manufacturing area and complexity, generally limits the extent of applicability thereof in practice. Similarly, the traditional burn-in process that is used to accelerate extrinsic failures is reaching a point where it is raising a number of complications and is becoming more difficult to implement with each successive process generation. In some instances, burn-in is believed to cause lifetime reliability problems itself, as a result of which, there has been an increased degree of interest in developing alternative techniques for improving the chip lifetime reliability without the burn-in process in recent years.
There is a significant amount of cost associated with the process variation in technologies, especially at levels of 32 nm and below. Lost yield due to process variability causes millions of dollars in wasted expenditures every year per production line. There is significant cost and problems associated with lost yield due to process variation in current and next generation technologies. These include timing and associated functionality problems, performance reduction due to the timing changes, increase in chip footprint due to the additional blocks, ability to handle only single fault and single type of fault due to lack of intelligence in the current approaches to dealing with variability.
In order to provide clear advantages over the current state of the technology, in accordance with the invention, there is proposed a technique that is adapted to alleviate lifetime reliability and process variability issues through the intermediary of three-dimensional (3D) integration. Even though the motivation for 3D integration has been largely interconnect-driven and packaging-oriented, 3D integration can provide further broader advantages when effectively utilized.
Chip yield, which is the fraction of functional chips among all manufactured chips, is a key factor in determining chip cost. From a manufacturing point of view, per-wafer production cost of semiconductor chips cannot be lowered below a certain level. Since the total production cost must be recouped from the sale of functional chips, a low chip yield invariably drives up the unit cost of the chip.
State-of-the-art semiconductor chips that provide superior performance often run into a high production cost due to low chip yield. This is because state-of-the-art semiconductor chips, in order to deliver superior performance than more common economical chips, tend to utilize a large chip area as well as aggressively scaled lithographic dimensions and processing techniques that have not fully matured or stabilized. Thus, the more aggressive the unit process technology employed in manufacturing a chip, and the larger the area of the chip, the lower the chip yield and the higher the cost of the chip.
In order to improve chip yield, redundancy repair components are often fabricated on a chip. This is almost universally done for array structures such as dynamic random access memory (DRAM) arrays and static random access memory (SRAM) arrays. Incorporation of redundant rows or redundant columns is easy to implement in an array structure.
For logic blocks, redundancy is much harder to implement since components of logic blocks are much less repetitive. Prediction of a high failure rate area is mostly a futile exercise since most of the logic block components have insignificant failure rates. Thus, building redundancy for logic blocks is much less effective than for an array structure, as well as requiring much more area than redundancy repair components for the array structure. In other words, the area penalty associated with building redundancy repair components for logic blocks is unacceptably high.
Normal chips containing multiple processor cores on a semiconductor substrate could include extra processor cores for redundancy repair to improve yield. However, the total area of the extra processor core including the areas of caches and bus interconnect logic circuits is substantial for each extra processor core. Further, considering that the caches and the bus interconnect logic circuits typically have a high yield, the areas occupied by the caches and the bus interconnect logic circuits are wasted area that typically does not contribute to improved yield yet increases the total chip area.
Further, design requirements typically call for a number of processor cores that is a power of two, i.e., 2, 4, 8, etc., which typically fits into natural floor planning pattern for chips. Adding extra processor cores for redundancy repair generally breaks this natural floor planning pattern. For these reasons, addition of extra processor cores into a semiconductor chip is, in general, problematic.
However, providing a mechanism for repairing a chip has grown in importance since the number of processor cores per chip continues to increase. “All good chips” in which all processor cores are functional becomes more challenging with the increase in the number of processor cores.
In view of the above, there exists a need to provide improved yield to a semiconductor chip having multiple processor cores.
Specifically, there exists a need to provide a structure having a repair capability to semiconductor chips having multiple processor cores and methods of manufacturing the same.